| 31 | 30 | 29 | 28 | 27 | [26:0] | |
| Bit name | NVD | FF | HF | EF | 0 | FIFODATA |
| R=READ W=WRITE | R | R | R | R | R | R |
Access time to EFIFO bank is about five(5) times faster than for the DFIFO bank. Therefore, it is suggested to use EFIFO when using the ROCK in a stand-alone environment (w/o CBUS).
EFIFO specific notes:
See also the ROCK sub-frame documentation.
Back to FIFO page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | FLTRST | INTRST | AUXRST | DFIFO | EFIFO | XINTF | TFIFO | CINTF |
| R=READ W=WRITE | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Power-up status | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
CINTF must be asserted in order to read out the DFIFO from the VME.
When TKNDIS and FLTRST are both not asserted, a CRST on CBUS cable will ALWAYS reset:
INFO and
FIFO pages power up to an unknown state.
After power up, the Reset register must be deasserted (by loading 0xFF) for at least 250 ms.
Eventually,a short reset should be applied.
Back to INTERNAL page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | DFF | DHF | DEF | EFF | EHF | EEF | TEF | TFF |
| R=READ W=WRITE | R | R | R | R | R | R | R | R |
| Power-up status | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 |
See also the FIFO page.
Back to INTERNAL page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | WATCHDOG | |||||||
| R=READ W=WRITE | R/W | |||||||
| Power-up status | 0 | |||||||
Watchdog logic asserts HALT
if an AUXbus transaction takes more than programmed.
Timeout = WATCHDOG*(2**WSCALE)*100 ns
Setting this register to 0x00 disables the watchdog.
Back to INTERNAL page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | 1 | 1 | EFMODE | BOE | TKNDIS | INTTRG | DIAG | |
| R=READ W=WRITE | R | R | R/W | R/W | R/W | R/W | R/W | |
| Power-up status | 1 | 1 | 0 | 0 | 0 | 0 | 0 | |
| 0 | EFIFO flags are in control of AUXbus operation EFIFO is always written in, except during a Sync Cycle (EFIFO is a copy of DFIFO) |
| 1 | DFIFO flags are in control of AUXbus operation EFIFO is written only during a Sync Cycle |
| 2 | DFIFO flags are in control of AUXbus operation EFIFO is always written in |
| 3 | DFIFO flags are in control of AUXbus operation EFIFO is never written in |
See FIFO page for details.
See also FLTRST.
Back to INTERNAL page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | TKNIN | TKNOUT | CEOB | CERR | CRST | CRNGT | CBUSY | CTRGV |
| R=READ W=WRITE | R | R | R | R | R | R | R | R |
| Power-up status | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
CSR1 displays the main CBUS signals on-board.
Back to INTERNAL page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | 1 | EFWREN | AUXON | TIMEOUT | ELAPSED | WSCALE | ||
| R=READ W=WRITE | R | R | R | R | R/W | R/W | ||
| Power-up status | 1 | 0 | 1 | 1 | 1 | 0 | ||
Back to INTERNAL page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | ELAPSEDTIME | |||||||
| R=READ W=WRITE | R | |||||||
| Power-up status | 0 | |||||||
Elapsed register is reserved for performance monitoring. It makes possible to misure in real-time the AUXbus bandwith usage, without overhead.
Elapsed time = ELAPSEDTIME*(2**WSCALE)*100 ns
Performance monitoring also uses ELAPSED (bit) and EFMODE to trap subevents in the EFIFO bank.
Back to INTERNAL page.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit name | HALT | BUSY | SYNCHF | XBUSY | XBERR | 1 | TEST | |
| R=READ W=WRITE | R | R | R | R | R | R | W | |
| Power-up status | 1 | 1 | 1 | 1 | 1 | 1 | 3 | |
HALT is a unrecoverable error. It stops data-taking activity.
If the condition which caused HALT persistes,
HALT will be immediatly reasserted after be cleared.
Always investigate about the reason of HALT!
BUSY is mainly a replica of the XBUSY line on the AUXbus. It notifies the Trigger Supervisor that at least one slave is running out of memory and trigger generation should be suspended.
BUSY is also asserted when the ROCK's Trigger FIFO goes full.
BUSY is a real-time flag, i.e. it toggles between TRUE and FALSE as needed and no minimum pulse width is guaranteed.
BUSY is always asserted in case of HALT.
When INTTRG is asserted, the NIM front panel inputs are isolated
and both Trig and SyncR pulses can be sent by writing specific codes into TEST.
Refrain from reset-and-try-again!
TEST codes are:
Back to INTERNAL page.
| 15 | 14 | 13 | 12 | [11:0] | |
| Bit name | 0 | 0 | TFF | LINK | QTRG |
| R=READ W=WRITE | R | R | R | R | R |
Back to INFO page.
| [15:12] | [11:0] | |
| Bit name | CSTATE | PTRG |
| R=READ W=WRITE | R | R |
Back to INFO page.
| [15:14] | 13 | 12 | 11 | 10 | 9 | 8 | [7:4] | [3:0] | |
| Bit name | 0 | SOF | EOF | 0 | SYNCRESPF | ROCKSFAIL | SLVSFAIL | LWADD | XADD |
| R=READ W=WRITE | R | R | R | R | R | R | R | R | R |
Back to INFO page.
| 15 | [14:12] | [11:0] | |
| Bit name | LAST | CRADD | GOLDENREF |
| R=READ W=WRITE | R/W | R/W | R/W |
Can only be written in DIAG mode.
Back to INFO page.
| Top of the page. | Back to the ROCK documentaion. | Send comments to: Igor Sfiligoi |
| Created | : | 21.1.1997 |
| Last modified | : | 4.4.1997 |