*
* Questa e' la MODULE LIST di FINUDA
*
*
* SM&PG: modified on 6/12/2002 
*

{CAMAC

 WARNING: This field MUST be before all the CAMAC module

 CBD base (0:not present) =de800000

}

{Corbo

 base =debbbb00

CH1
 status1 (0:enable, 1:disable) =0
 set counter1 (0:trigger, 1:busy) =1
 count1 =0
 dead1 =0

CH2
 status2 (0:enable, 1:disable) =0
 set counter2 (0:trigger, 1:busy) =1
 count2 =0
 dead2 =22

CH3
 status3 (0:enable, 1:disable) =0
 set counter3 (0:trigger, 1:busy) =0
 count3 =0
 dead3 =3

CH4
 status4 (0:enable, 1:disable) =0
 set counter4 (0:trigger, 1:busy) =1
 count4 =0
 dead4 =4

}

{Tdc96VME
 
 ATT: automatic address base:0x80000*slot, memory:0x20000*slot
      Only Tdc96 in remote VIC cages

 Vic cage (3:d, 0:not present) =0
 VME slot (6:21) =0
 mode (0:common stop, 1:common start) =0
 c_start_tout (0:16) =0
 f_clear_win (0:16) =0
 h_lead_rec (0:disable, 1:enable) =1
 h_trai_rec (0:disable, 1:enable) =0
 full_scale_range (0:32760 ns) =32760
 lifo_dept (1:15) =1
}

{Vic50 (8250)

 base =de700000

 Crate branch of VMV Slaves (0:not present, 1:present)
 WARNING: don't use the same crate number on different crate
          also if they are on different vic50 brach

 slave crate 0 =0 don't use
 slave crate 1 =0 don't use
 slave crate 2 =0 don't use
 slave crate 3 =0
 slave crate 4 =0
 slave crate 5 =0
 slave crate 6 =1
 slave crate 7 =0
 slave crate 8 =0
 slave crate 9 =0
 slave crate a =0
 slave crate b =0
 slave crate c =0
 slave crate d =0
 slave crate e =0 don't use
 slave crate f =0 don't use
 
}


{PcoVME

 base =de242000
 
 delay (0:127) =100

}

{PreVME      NB: never desable this module !!

 base =de442100

 Trigger flag (0:modlist programmed, 1:trigger programmed)
 trigger =1

 
 prescaling factors (range from 1 up to 16777216, 1 means no prescal)
 CH1 =1000
 CH2 =1000
 CH3 =1000

}


{MultVME selector

 base =de242000
 
 thresholds (0:15)
 CH1
    low  =1
    high =3
 CH2
    low  =3
    high =5

}


{ScalVME

 base =de554400

 Channels mask (0:not coupled, 1:coupled)
 couple 0-1 =0
 couple 2-3 =0
 couple 4-5 =0
 couple 6-7 =0
 couple 8-9 =0
 couple a-b =0
 couple c-d =0
 couple e-f =0

}

{PattVME Unit

 base =de444400

}

{IorVME

 base =dea00000
 strobe (1:negative, 0:positive) =1

 Status mode (4:out not strobed, 12:out strobed, 13:in ext strobed)
 status 0 =12 out
 status 1 =12 out
 status 2 =12 out
 status 3 =12 out
 status 4 =12 out
 status 5 =12 out
 status 6 =12 out
 status 7 =12 out
 status 8 =13 in
 status 9 =13 in
 status a =13 in
 status b =13 in
 status c =13 in
 status d =13 in
 status e =13 in
 status f =13 in

 Output pattern
 ch0 =1
 ch1 =1
 ch2 =1
 ch3 =1
 ch4 =0
 ch5 =0
 ch6 =0
 ch7 =0
 ch8 =0
 ch9 =0
 cha =0
 chb =0
 chc =1
 chd =1
 che =1
 chf =1
 

}

{PluVME      NB: never desable this module !!

 base =de555000

 Configuration mode (12:strobed mode, 780:normal mode)
 config (0:2048) =780

 Trigger flag (0:preprogrammed plu, 1:trigger plu)
 trigger =1

}


{PluVME

 base =de033000

 Configuration mode (12:strobed mode, 780:normal mode)
 config (0:2048) =12
 
 Trigger flag (0:modlist programmed plu, 1:trigger plu)
 trigger =0
 
}plufile1.dat-plufile2.dat-


{DiscfVME

 base =d2800000

 thresholds high (0:280) mV 
 thh_0  =50
 thh_1  =50
 thh_2  =50
 thh_3  =50
 thh_4  =50
 thh_5  =50
 thh_6  =50
 thh_7  =50
 thh_8  =50
 thh_9  =50
 thh_10 =50
 thh_11 =50
 thh_12 =50
 thh_13 =50
 thh_14 =50
 thh_15 =50
 thh_16 =50
 thh_17 =50
 thh_18 =50
 thh_19 =50
 thh_20 =50
 thh_21 =50
 thh_22 =50
 thh_23 =50
 thh_24 =50
 thh_25 =50
 thh_26 =50
 thh_27 =50
 thh_28 =50
 thh_29 =50
 thh_30 =50
 thh_31 =50

 thresholds groups low (0:51) mV 
 thl_0_7     =5
 thl_8_15    =5
 thl_16_23   =5
 thl_24_31   =5

}

{DelCAMAC 

 crate =0
 station =15

 Delay value (0:255)
 delay CH0 =60
 delay CH1 =60
 delay CH2 =60
 delay CH3 =60
 delay CH4 =60
 delay CH5 =60
 delay CH6 =60
 delay CH7 =60
 delay CH8 =60
 delay CH9 =60
 delay CH10 =60
 delay CH11 =60
 delay CH12 =60
 delay CH13 =60
 delay CH14 =60
 delay CH15 =255

}

{DelgVME and Gate 

 base =d2002200 

 mode (0:normal, 1:common test modde, 2:coupled 1I-2O) =0
 mux (0:7) =0

 Delay & gate (0:255)
 CH0 Delay =0   Gate =255
 CH1 Delay =10  Gate =250
 CH2 Delay =50  Gate =200
 CH3 Delay =100 Gate =150
 CH4 Delay =150 Gate =100
 CH5 Delay =200 Gate =50
 CH6 Delay =250 Gate =10
 CH7 Delay =255 Gate =0

}

{IorgCAMAC

 crate =1
 station =22

 strobe mode (0:negative signal, 1:positive signal) =0

 Status mode 
 (for pos sig strobe 4:out not strobed, 12:out strobed, 13:in ext strobed)
 (for neg sig strobe 6:out not strobed, 14:out strobed, 15:in ext strobed)

 status 0 =15
 status 1 =14
 status 2 =15
 status 3 =14
 status 4 =6
 status 5 =14
 status 6 =6
 status 7 =15
 status 8 =6
 status 9 =6
 status a =6
 status b =6
 status c =6
 status d =6
 status e =6
 status f =6

 Output pattern 
 ch0 =1
 ch1 =1
 ch2 =1
 ch3 =1
 ch4 =1
 ch5 =1
 ch6 =1
 ch7 =1
 ch8 =1
 ch9 =1
 cha =1
 chb =1
 chc =1
 chd =1
 che =1
 chf =1

}

{OrgCAMAC     NB: never desable this module !!

             (remind to check trigger flag at the end of list)
 crate =1
 station =1

 
 Output pattern
 ch0 =1
 ch1 =1
 ch2 =1
 ch3 =0
 ch4 =0
 ch5 =0
 ch6 =0
 ch7 =0
 ch8 =0
 ch9 =0
 cha =0
 chb =0
 chc =0
 chd =0
 che =0
 chf =1

 pulse mode (1:on, 0:off) =0

 Trigger flag (0:modlist programmed, 1:trigger programmed)
 trigger =1

}


{MaluCAMAC

 crate =1
 station =20

 memory mode (0:disable, 1:enable) =1
 cluster mode (0:disable, 1:enable) =0

}


{ScalCAMAC

 crate =1
 station =2
 channels =16
}


{MeanCAMAC

 crate =1
 station =3

 channels pattern (0: disabled, 1: enabled)
 ch0  =1
 ch1  =1
 ch2  =1
 ch3  =1
 ch4  =1
 ch5  =1 
 ch6  =1
 ch7  =1
 ch8  =1
 ch9  =1
 ch10 =1
 ch11 =1
 ch12 =1
 ch13 =1
 ch14 =1
 ch15 =1

}


{PluCAMAC

 crate =1
 station =9

 read switch (0:normal, 1:continuous) =0
 mode (0:overlap, 1:strobe, 2:strobe+shape) =0
 
 Trigger flag (0:preprogrammed plu, 1:trigger plu)
 trigger =0

}plucamac.dat

{TdcdCAMAC
 
 crate =1
 station =9

 mode (0:common stop, 1:common start) =1
 c_start_tout (0:7) =0
 h_lead_rec (0:disable, 1:enable) =1
 h_trai_rec (0:disable, 1:enable) =1
 e_ch_test (0:disable, 1:enable) =0
 o_ch_test (0:disable, 1:enable) =0
 trig_mode (0:pulse, 1:latch) =0
 test_hit_d (0:3) =0
 test_hit_b (0:3) =0

}

{DiscCAMAC

 crate =1
 station =18

 threshold =50
}

{AdcCAMAC

 crate =1
 station =7

}

{TdcaCAMAC

 crate =1
 station =13

}

{Pre423CAMAC

 crate =1
 station =16

 clock mode (0:single, 1:1us, 2:1ms, 3:external) =3
 load mode (0:single, 1:repetitive) =1

}


{Adc9uVME

 base =de550000
  
 board nr (0:31) =1 
 offset current (0:2047) =700

 channel group enable (0:disable, 1:enable)
 group 0-7   =1
 group 8-15  =1 
 group 16-23 =1 
 group 24-31 =1
 group 32-39 =1 
 group 40-47 =1 
 group 48-55 =1 
 group 45-63 =1

 channel register 0:31
 zero/over suppression (1:enable, 0:disable) =1
 pedestal suppression (1:enable, 0:disable) =1

 channel register 32:63
 zero/over suppression (1:enable, 0:disable) =1
 pedestal suppression (1:enable, 0:disable) =1

 low threshold (if 0 set to calculated) =0

}

{Tdc9uVME

 base =deaa0000
  
 board nr (0:31) =0 
 range (100ns:800ns) =400

 channel group enable (0:disable, 1:enable)
 group 0-7   =1
 group 8-15  =1 
 group 16-23 =1 
 group 24-31 =1
 group 32-39 =1 
 group 40-47 =1 
 group 48-55 =1 
 group 45-63 =1

 channel register 0:31
 zero/over suppression (1:enable, 0:disable) =1
 pedestal suppression (1:enable, 0:disable) =1

 channel register 32:63
 zero/over suppression (1:enable, 0:disable) =1
 pedestal suppression (1:enable, 0:disable) =1

 common start (0:disable, 1:enable) =0
 common stop (0:disable, 1:enable) =1

 low threshold (if 0 set to calculated) =0
}

{Tdc64VME

 base =de310000          board nr (1:9) 1  
 
 channel enable (1: enable, 0: disable)
 ch0  =1 ch1  =1 ch2  =1 ch3  =1 ch4  =1 ch5  =1 ch6  =1 ch7  =1
 ch8  =1 ch9  =1 ch10 =1 ch11 =1 ch12 =1 ch13 =1 ch14 =1 ch15 =1
 ch16 =1 ch17 =1 ch18 =1 ch19 =1 ch20 =1 ch21 =1 ch22 =1 ch23 =1
 ch24 =1 ch25 =1 ch26 =1 ch27 =1 ch28 =1 ch29 =1 ch30 =1 ch31 =1

 ch32 =1 ch33 =1 ch34 =1 ch35 =1 ch36 =1 ch37 =1 ch38 =1 ch39 =1
 ch40 =1 ch41 =1 ch42 =1 ch43 =1 ch44 =1 ch45 =1 ch46 =1 ch47 =1
 ch48 =1 ch49 =1 ch50 =1 ch51 =1 ch52 =1 ch53 =1 ch54 =1 ch55 =1
 ch56 =1 ch57 =1 ch58 =1 ch59 =1 ch60 =1 ch61 =1 ch62 =1 ch63 =1
 
 mode (1:common stop, 0:common start) =1 
 h_ris_rec (0:disable, 1:enable) =1
 h_fal_rec (0:disable, 1:enable) =0
 rec_hit(0:15) =0 (0 means 1 event, 15 means 16 events)
 full_scale_range (32:32768 ns, only power of 2 allowed) =4096 
 
}                      


{Plu512VME

 base =ded00d00

 ATT: OUTPUT is f2(f1(a,b)f0(c,d))
 Functions (0:or,1:and)

 f0 =0
 f1 =0
 f2 =0

}
  

{CfdCamac

 crate =1
 slot =10

 majority (0:255) =3 
 output width (60:300 ns) =100
 dead time (60:300 ns) =100 

 Channels configuration (0:not inhibit, 1:inhibit)
                        (threshold 0:1024 mV)
  inhibit ch 0 =1
  threshold ch 0 =100
  inhibit ch 1 =1
  threshold ch 1 =100
  inhibit ch 2 =1
  threshold ch 2 =100
  inhibit ch 3 =1
  threshold ch 3 =100
  inhibit ch 4 =1
  threshold ch 4 =100
  inhibit ch 5 =1
  threshold ch 5 =100
  inhibit ch 6 =1
  threshold ch 6 =100
  inhibit ch 7 =1
  threshold ch 7 =100
  inhibit ch 8 =1
  threshold ch 8 =100
  inhibit ch 9 =1
  threshold ch 9 =100
  inhibit ch 10 =1
  threshold ch 10 =100
  inhibit ch 11 =1
  threshold ch 11 =100
  inhibit ch 12 =1
  threshold ch 12 =100
  inhibit ch 13 =1
  threshold ch 13 =100
  inhibit ch 14 =1
  threshold ch 14 =100
  inhibit ch 15 =1
  threshold ch 15 =100
}

{Cfd671

 crate =1
 slot =1
 
 ch1_th=30  (threshold must be greater than 5 mV)
 ch2_th=30
 ch3_th=30
 ch4_th=30
 ch5_th=30
 ch6_th=30
 ch7_th=30
 ch8_th=30
 ch9_th=30
 ch10_th=30
 ch11_th=30
 ch12_th=80
 ch13_th=150
 ch14_th=150
 ch15_th=150
 ch16_th=150

 ch1_en=1  (1:enable 0: disable)
 ch2_en=1
 ch3_en=1
 ch4_en=1
 ch5_en=1
 ch6_en=1
 ch7_en=1
 ch8_en=1
 ch9_en=1
 ch10_en=1
 ch11_en=1
 ch12_en=1
 ch13_en=1
 ch14_en=1
 ch15_en=1
 ch16_en=1

 output width 0:7 (24:400 ns)=200
 output width 8:15 (24:400 ns)=200
 
 ex_majority (0:43) =1             (0: exclude this cfd from ex_majorty; 
                                    1-43: ex_majority threshold)
 in_majority (1:16) =1
 
 output delay 0:7   =35        (35:535 ns step 10ns)
 output delay 8:15  =35       (35:535 ns step 10ns)
 delout width 0:7   =250             (10:250 ns )
 delout width 8:15  =250             (10:250 ns )
} 


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